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Altera_Forum's avatar
Altera_Forum
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18 years ago

EDA gate level simulation

when i do a timing simulation using Quartus (and not third party EDA tool), i am able to notice all the delays like the output changing some time after the positive edge of clock (which in a function...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

If you don't see any delay in timing simulation, there is a possibilty that your SDO file is not annotated correctly during timing simulation. How do you run the simulation? Try to use the native link feature (Tools->EDA Simulation Tools -> RUN EDA Gate Level SImulation) as a reference whether you setup the *.do script correctly or not. Do you still get zero delay using native link? This is unlikely.

Refer the native link feature at http://www.altera.com/literature/hb/qts/qts_qii53001.pdf for more information.