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Altera_Forum
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13 years ago

Easy way to attach address and data bus to the outside world ?

Hi All, An SPOC NIOS controller has been built in Verilog that includes SDRAM, and an instance has been added to a top level block schematic. The NIOS controller exposes about 40 signals a...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi Mark,

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Is it possible to access I/O pins from a subordinate Verilog block, or does all I/O have to de done at the top level ?

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In simulation you can access signals anywhere within the design. However, for synthesis, the signals that route to pins have to be part of the top-level entity.

However, with SignalTap II (Altera's logic analyzer) you can probe pretty much any signal within the design.

For example, you can use Modelsim for design and simulation, and then SignalTap II to confirm your logic in hardware.

Cheers,

Dave