Dynamic width of inputs in VHDL.

Hm, I seem to still have the same problem, I declared n_t is natural range 0 to 2000 in a library

ENTITY logic IS

PORT( clock, reset, readyfsmtologic: IN STD_logic;

n,k: in n_t;

datafsmtologic : in std_logic_vector(63 downto 0);

datalogictofsm : out std_logic_vector(63 downto 0);

donelogictofsm : out std_logic

);

END logic;

FUNCTION main (poly_in00:std_logic_vector ; nf, kf: n_t) RETURN std_logic_vector is

variable out:std_logic_vector(2*nf + 1 downto 0):=(others=>'0');

begin

--function

end

It says that the line

variable out:std_logic_vector(2*nf + 1 downto 0):=(others=>'0');

Error (10779): VHDL error at logic.vhd(118): expression is not constant

Fred