Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Dynamic width of inputs in VHDL.

Hi, I'm finishing my final year project and while connecting a lot of components together I ran into a problem I missed while writing the first component. I would want to dynamically change the w...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

If n is static per simulation run, then use a generic.

If n needs to change during the simulation, then either dynamically create the std_logic_vector, or use a vector with a width that is the maximum value for n. In that case, use a subtype for port n that restricts the values for n, eg., subtype n_t is natural range 0 to 2000.

Cheers,

Dave