Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Dynamic width of inputs in VHDL.

Hi, I'm finishing my final year project and while connecting a lot of components together I ran into a problem I missed while writing the first component.

I would want to dynamically change the width of my std_logic_vector inputs or a least create signals that have dynamic width depending on an inputed natural, example:

LIBRARY ieee;

USE ieee.std_logic_1164.all;

use ieee.numeric_std.all;

entity test1111 is

port(

n: in natural

);

end test1111;

architecture archtest of test1111 is

signal lk:std_logic_vector(n downto 0);

begin

end archtest;

In this example I have to following problems: the signal lk gives the error: expression is not constant vhdl., does this mean that signals in vhdl HAVE to have constant widths?

I got the same problem when declaring a function:

function main (poly_in00:std_logic_vector ; n,k: natural) RETURN std_logic_vector is

variable vPoly : std_logic_vector(n downto 0) := (others => '0');

Now, normally I would use the 'length parameter in a function, but in this case I have a 2000 wide std_logic_vector but only need a part of it(n) for calculations

It would be awesome if anyone could help, thanks a lot!

Fred

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    If n is static per simulation run, then use a generic.

    If n needs to change during the simulation, then either dynamically create the std_logic_vector, or use a vector with a width that is the maximum value for n. In that case, use a subtype for port n that restricts the values for n, eg., subtype n_t is natural range 0 to 2000.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Hm, I seem to still have the same problem, I declared n_t is natural range 0 to 2000 in a library

    ENTITY logic IS

    PORT( clock, reset, readyfsmtologic: IN STD_logic;

    n,k: in n_t;

    datafsmtologic : in std_logic_vector(63 downto 0);

    datalogictofsm : out std_logic_vector(63 downto 0);

    donelogictofsm : out std_logic

    );

    END logic;

    FUNCTION main (poly_in00:std_logic_vector ; nf, kf: n_t) RETURN std_logic_vector is

    variable out:std_logic_vector(2*nf + 1 downto 0):=(others=>'0');

    begin

    --function

    end

    It says that the line

    variable out:std_logic_vector(2*nf + 1 downto 0):=(others=>'0');

    Error (10779): VHDL error at logic.vhd(118): expression is not constant

    Fred
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Rather than posting code snippets, could you post a zip file with a minimal set of files.

    Note, try not to use reserved keywords in your code, otherwise you will get weird errors - 'out' is a keyword.

    I don't think that is your error, but its a good thing to keep in mind.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You cannot dynamically resize signals while a simulation is running. They have to be fixed size during a run, so you will have to go with the generic suggestion and make the size of the vector the worst case size. Think about it- trying to resize a signal is like trying to add more wires to a circuit while it is switched on, which is physically impossible.

    The only way you can "dynamically" change an array size is with a pointer type, but you cannot synthesise them and are for testbenching only.