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Altera_Forum
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13 years ago

Dynamic width of inputs in VHDL.

Hi, I'm finishing my final year project and while connecting a lot of components together I ran into a problem I missed while writing the first component. I would want to dynamically change the w...
Altera_Forum's avatar
Altera_Forum
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13 years ago

You cannot dynamically resize signals while a simulation is running. They have to be fixed size during a run, so you will have to go with the generic suggestion and make the size of the vector the worst case size. Think about it- trying to resize a signal is like trying to add more wires to a circuit while it is switched on, which is physically impossible.

The only way you can "dynamically" change an array size is with a pointer type, but you cannot synthesise them and are for testbenching only.