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Altera_Forum
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15 years ago

Dynamic Bus sizing problem with narrow master and wide slave

Hi, In my sheme an avalon master is connected to SDRAM slave in the SOPC builder. Both are 16 bit wide. When the master's clock is 25MHz and SDRAM clock is 100MHz writes from master to SDRAM are...
Altera_Forum's avatar
Altera_Forum
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15 years ago

This to update that the problem got solved by setting "Extarct Verilog State Machines" setting to OFF. This thread can be considered closed. Thanks to all.