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Altera_Forum's avatar
Altera_Forum
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14 years ago

duplicate names

Hi,

I have a problem with duplicate names of files and entity in me project.

I have compiled project with 2 blocks : UART and P-Block.

I want to add a new UART block ( from another project ) to me project.

The new UART is similar to the first one but not exactly the same. The name of file and entity of it's building blocks is the same as the first one but different in their functional.

The result is compilation errors duo to duplicate names of the files and entity between the UARTs.

Can I add the new UART to the project without changing the names?

BIG THX,

Guy.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Assuming VHDL:

    You could put the second UART in another library and then in the VHDL you can differentiate between them when you instantiate them using direct instantiation:

    UART1_inst : entity uart1_library.uart

    port map (

    ...

    UART2_inst : entity uart2_library.uart

    port map (

    ...

    etc
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    It's not working. There is a way to do this using attributes in VHDL?

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    There are no attributes for library naming.

    Have you created two separate libraries? are you sure you're calling them correctly? how is it not working? You are not very clear with your questions.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    i never had much success with VHDL libraries in Quartus

    i would try and create a .qxp of one of the UARTs to avoid the name clashes