Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Dual ported ram in modelsim

I have problems accessing dual ported ram in Modelsim. My ram looks like this: component ram_megafunction is port ( address_a : IN STD_LOGIC_VECTOR (7 DOWNTO 0...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

It seems that you have multiple drivers on some signals. Forcing a signal to 0 and 1 at the same time will give an X.

You can check a few things:

- do you have only one connection on data_a and data_b?

- are you trying to write two different values from each port at the same address?

- do you have only one connection to data_out?