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Altera_Forum
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17 years ago

Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

I'm using the Quartus II template for a true Dual port RAM with single clock, when I simulate it in Quartus simulator the behavior is ok, and synthsised correctly to the memory bits in a Cyclone III ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Using the template would be fine if it weren't broken for simulation. Using the Verilog version requires me to have both a Verilog and VHDL simulation license for ModelSim, doesn't it?

Moreover, instantiating the primitive causes simulations to run significantly slower. I'd prefer to use a configuration switch in the top level on a generic dual port RAM in VHDL than do mixed-mode HDL.

In the end, the template should be changed to allow proper simulation in either language.