Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

Using configurations and multiple architectures, I was able to do both proper simulation and synthesis.

I have attached my example with both a top level instantiation for synthesis and a simulation showing proper use.

The configuration is very simple, but if you want to get more creative you can read more about them here:

http://www.cs.umbc.edu/help/vhdl/design.html#config

Let me know if this helps you out or is a feasible solution for your needs.