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Altera_Forum
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17 years ago

Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

I'm using the Quartus II template for a true Dual port RAM with single clock, when I simulate it in Quartus simulator the behavior is ok, and synthsised correctly to the memory bits in a Cyclone III ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

Look at that. I suppose I had never been actually using the dpram models for dual-write purposes. This sure is a shame.

I knew that driving the same signal from different processes was an issue for synthesis, but I thought simulation would resolve down to the address location and not just the signal itself.

Does Altera have any intention on fixing this, or is their solution to instantiate an altsyncram?