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Altera_Forum
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17 years ago

Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

I'm using the Quartus II template for a true Dual port RAM with single clock, when I simulate it in Quartus simulator the behavior is ok, and synthsised correctly to the memory bits in a Cyclone III ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

You r right, I discovered that the .vho is used in gate level simulation and not with RTL.

I think megafunctions work propably, except that the dual port ram generated needs 2 clocks to read the contents of 2 addresses in memory, unlike writing, which takes only 1 clock to write in 2 addresses simultenously.

So, in case of reading, it's the same as single port ram.