Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

This is a known problem with the dual-port RAM template. It has two process statements that write to the same signal (a 2-D array of std_logic, a resolved type). When both process statements drive the signal, it results in logic contention that shows up as X.

Unfortunately, the template can't use a shared variable because Quartus II doesn't infer RAMs from shared variables. It also can't move the two writes into the same process because that would imply a priority between the two writes that doesn't exist in the underlying hardware.