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Altera_Forum
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17 years ago

Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

I'm using the Quartus II template for a true Dual port RAM with single clock, when I simulate it in Quartus simulator the behavior is ok, and synthsised correctly to the memory bits in a Cyclone III ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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There's a file (.vho) automatically created in the simulation/modelsim folder that contains an auto generated code of my test bench with instantiation of altsyncram, i think ModelSim uses this file.

:(

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The .vho file is a gate level netlist generated by Quartus.

I believe Modelsim will use your original source files (.vhd) unless you explicity compile the .vho file for simulation. Your original post stated "ModelSim RTL simulation" i.e. not gatelevel.

Are you 100% certain that you are not using the RTL level .vhd compiled files in your modelsim simulation? If you are using the .vhd then modelsim will infer it's own memory structures.