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Altera_Forum
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17 years ago

Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

I'm using the Quartus II template for a true Dual port RAM with single clock, when I simulate it in Quartus simulator the behavior is ok, and synthsised correctly to the memory bits in a Cyclone III ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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There's a file (.vho) automatically created in the simulation/modelsim folder that contains an auto generated code of my test bench with instantiation of altsyncram, i think ModelSim uses this file.

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Ah, are you doing gate-level simulation under ModelSim? I missed that, I thought you were doing HDL/RTL level simulation.