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Altera_Forum
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17 years ago

Dual port RAM in Quartus II 7.2, different behavior on ModelSim than Quartus simulato

I'm using the Quartus II template for a true Dual port RAM with single clock, when I simulate it in Quartus simulator the behavior is ok, and synthsised correctly to the memory bits in a Cyclone III ...
Altera_Forum's avatar
Altera_Forum
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17 years ago

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However, when I simulate the same code using ModelSim RTL simulation the behavior is different. The problem arises when I try to write to both ports at the same time at two different addresses, where the data is written as 'X'!!. Note that: the whole memory is initially zeros.

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Not sure if this is your problem, but note that ModelSim doesn't know, and doesn't assume by default that your memory is initially zero.

For ModelSim, every register and RAM is initially X by default.