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Altera_Forum
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9 years ago

Dual Clock FIFO Implementation VHDL

Hi, I'm pretty newto VHDL and I'm trying to implement a Dual Clock Synchronous FIFO but I'm getting loads of error mainly things like: Error (10822): HDL error at FIFO.vhd(57): couldn't imp...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

This looks very much like a software approach to digital electronics - it will not work. You cannot have a register that is clocked from two clocks in FPGAs. And reading registers in one clock domain that is registered in another clock domain is very poor practice unless you're doing safe clock domain crossing.

Altera already provides a dual clock FIFO for free - check out the IP catalog.