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Altera_Forum
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12 years ago

DS18b20+VHDL

Hi all, I need a little help with my design,I would like connect sensor ds18b20 to the FPGA Altera DEOshematic.jpg I use the internal clock50MHz,I wrote some code but my design doesn't work.shows th...
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Altera_Forum
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12 years ago

But when is that reset asserted? Is it before the counter gets to 50000000? In simulation, if it went over 50mil, you would get an error (but hardware will just roll over - creating a hardware simulation missmatch).

If you use signal tap and find the counter is going over 50mil, you need to go back and re-run your simulations.