DRC check CDC-50001 does not work if the given bit is part of a vector?

For your reference:

VHDL file:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
 
entity cdc is
    port (
        clk1     : in  std_logic;
        clk2     : in  std_logic;
        rst      : in  std_logic;
        Output_A : out std_logic;
        Output_B : out std_logic
    );
end entity;
 
architecture rtl of cdc is
 
    signal locked     : std_logic;
    signal locked_reg : std_logic;
    signal clk1_pll   : std_logic;
 
    component pll is
        port (
            rst      : in  std_logic := 'X';  -- reset
            refclk   : in  std_logic := 'X';  -- clk
            locked   : out std_logic;         -- export
            outclk_0 : out std_logic          -- clk
        );
    end component pll;
 
begin
 
    u0 : component pll
        port map (
            rst      => rst,            --   reset.reset
            refclk   => clk1,           --  refclk.clk
            locked   => locked,         --  locked.export
            outclk_0 => clk1_pll        -- outclk0.clk
        );
 
    process (clk1_pll) is
    begin
        if rising_edge(clk1_pll) then
            locked_reg <= locked;
        end if;
    end process;
 
 
    process (clk2) is
    begin
        if rising_edge(clk2) then
            Output_A <= locked;
            Output_B <= locked_reg;
 
 
        end if;
    end process;
 
 
 
end architecture;

SDC file:

#**************************************************************
# Create Clock
#**************************************************************
 
create_clock -name {clk2} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk2}]
create_clock -name {clk1} -period 10.000 -waveform { 0.000 5.000 } [get_ports {clk1}]
 
 
#**************************************************************
# Create Generated Clock
#**************************************************************
 
create_generated_clock -name {u0|iopll_0|outclk0} -source [get_pins {u0|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|refclk[0]}] -duty_cycle 50/1 -multiply_by 6 -divide_by 6 -master_clock {clk1} [get_pins {u0|iopll_0|altera_iopll_i|twentynm_pll|iopll_inst|outclk[0]}] 
 
 
#**************************************************************
# Set Clock Latency
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Uncertainty
#**************************************************************
 
set_clock_uncertainty -rise_from [get_clocks {clk1}] -rise_to [get_clocks {clk1}]  0.030  
set_clock_uncertainty -rise_from [get_clocks {clk1}] -fall_to [get_clocks {clk1}]  0.030  
set_clock_uncertainty -fall_from [get_clocks {clk1}] -rise_to [get_clocks {clk1}]  0.030  
set_clock_uncertainty -fall_from [get_clocks {clk1}] -fall_to [get_clocks {clk1}]  0.030  
set_clock_uncertainty -rise_from [get_clocks {clk2}] -rise_to [get_clocks {clk2}]  0.030  
set_clock_uncertainty -rise_from [get_clocks {clk2}] -fall_to [get_clocks {clk2}]  0.030  
set_clock_uncertainty -fall_from [get_clocks {clk2}] -rise_to [get_clocks {clk2}]  0.030  
set_clock_uncertainty -fall_from [get_clocks {clk2}] -fall_to [get_clocks {clk2}]  0.030  
 
 
#**************************************************************
# Set Input Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Output Delay
#**************************************************************
 
 
 
#**************************************************************
# Set Clock Groups
#**************************************************************
 
set_clock_groups -asynchronous -group [get_clocks {clk1 u0|iopll_0|outclk0}] -group [get_clocks {clk2}]