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MOliv45's avatar
MOliv45
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6 years ago

DRC check CDC-50001 does not work if the given bit is part of a vector?

Summary: If the bit that is missing a synchronizer is part of a vector, the DRC check CDC-50001 FAILS. VHDL code: library IEEE; use IEEE.STD_LOGIC_1164.all; entity cdc is port ( clk1...
MEIYAN_L_Intel's avatar
MEIYAN_L_Intel
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6 years ago

Hi,

May I know the Quartus version and edition you are using?

I would like to test it on my side.

By reviewing you code "signal datao : std_logic_vector(0 to 1)", this is declaring the vector signal hold two bit while in your code "datao <= datai & '1'" and "Output_A <= datao(0)" show is only hold one bit.

Thanks

MOliv45's avatar
MOliv45
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6 years ago

Hi Mylee,

Yes, sure. I am using Quartus Prime Pro 19.3 Linux :)

In fact, in the previous code, you are right, the CDC was not detected because it had already two registers.

The reason I created this post was to reproduce the effect I see in a larger project, which would be difficult to share here.

I believe I have now managed to isolate the issue better. It seems that CDC-50001 DOES not work if the clock domain crossing is starting from an IP component pin. (nothing related to the vector, sorry)

For instance, the crossing from the IP pin "locked" to "Output_A" is not detected in the CDC-50001 DRC check, while the crossing from "locked_reg" to "Output_B" is.

Note that "clk1" and "outclk_0" belong to the same group, which is unrelated to clk2.

Therefore, the crossing from "locked" to "Output_A" should have been detected with the missing 1-bit synchronizer flag (DRC check CDC-50001)

This post is part of a larger effort in view of detecting mis-implemented clock domain crossings in larger projects we have here at CERN.

We like very much the Intel DRC check report, but we have leaned thorugh the experience in one of our projects that CDC-50001 does not work in this case, i.e. when the clock domain crossing involves an IP-component pin.

Can you help us out solving this issue?

Best Regards.

Marcos