DRAM interface with different clock domains (host writing, DAC reading)

Hi,

I need an external DRAM interface, the DRAM will be written by an external host with a data rate of 100MB and will be read and put out to a DAC with a data rate of 220MB. Data width of the external host and dac will be 32 bit.

As I have two DACs which shall run independently and Host-writing shall be possible while the DACs are running I think about taking four DRAMs, two for each DAC, so one can be written and one can be read at a time, not need to read and write to a DRAM at the same time. For the FPGA I have an eye on Arria V GX without hard memory controller (the small Arrias have only 2 controllers).

In an earlier design I used ALTERA's DDR2 SDRAM Controller in conjunction with dual-clock FIFOs to support the different clock domains.

Today there are so many options (RAM type, Quartus IPs, Multi port front-end) and also limitations (half-rate, full-rate) that I hope to get here some hints for a proper implementation.