DQ and DQS toggling issue on DDR PHY

Hi All,

We are facing an issue over our DDR PHY gate level simulations with SDF.

Only the PHY will be sitting on the FPGA (memory controller - memory models will be in testbench)

How do we club all the DQ pins / DQS pins so that they start toggling at same time.

I see a lot of toggling at irrelevant intervals because of which the data eye is minimal.

I have tried the option of Output Enable and DQ group but it did not have any effect.

Please give your suggestions.

Thanks