Altera_Forum
Honored Contributor
Honored ContributorDose quartus use any Black magic to constrain dcfifo(gray code pointer)?
First of all, sorry for my poor English, I'm from China.
The question is about gray code pointers in the async fifo. There are some similar post here: http://www.alteraforum.com/forum/showthread.php?t=44720 http://www.alteraforum.com/forum/showthread.php?t=37134 http://www.alteraforum.com/forum/showthread.php?t=3373 But I'm still confused To my knowledge, the delay of gray code pointer in the async fifo should not delay exceed 1 clk cycle of transmit clk, or the fifo will be failed. The delay is from register of source clk to register of destination clk, and exclude the clock skew. In the 《SCFIFO and DCFIFO IP Cores User Guide》，which is the altera megacore fifo user guide，it says that “ When using the Quartus II TimeQuest timing analyzer with a design that contains a DCFIFO block apply the following false paths to avoid timing failures in the synchronization registers: •For paths crossing from the write into the read domain, apply a false path assignment between the delayed_wrptr_g and rs_dgwp registers: set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g [*]}] -to [get_registers {*dcfifo*rs_dgwp*}] •For paths crossing from the read into the write domain, apply a false path assignment between the rdptr_g and ws_dgrp registers: set_false_path -from [get_registers {*dcfifo*rdptr_g [*]}] -to [get_registers {*dcfifo*ws_dgrp*}] The false path assignments are added through the HDL-embedded Synopsis design constraint (SDC) commands when you compile your design. The related message is shown under the TimeQuest timing analyzer report. Note: The constraints are internally applied but are not written to the Synopsis Design Constraint File (.sdc). To view the embedded-false path, type report_sdc in the console pane of the TimeQuest timing analyzer GUI. ” Question 1:Quartus automatically add set_false_path constrain to the gray code pointer, but how quartus confirm that the delay dose't exceed 1 clock period of source clock? Dose the fitter have some black magic to place the registers as close as possible? note: The set_false_path constrain has the highest priority Sometimes, users may use some gray code in design(e.g handwrite fifo......), and don't use ther altera's DCFIFO megacore. To constrain the 1 clock period dealy, in the timequest the closest constrain is set_max_delay. But if we use it to constrain the gray code pointer, it will calculate the clock skew also. This is totally wrong, but it should calcute the data path rout delay only. When I generate the async fifo in the vivado of xilinx , I can find that the tool generate the set_max_delay constrain in the XDC file, with the option "datapath_only". And I think that's what I need. Question 2:In this case, what constrain should be added in the SDC file?
