Dose quartus use any Black magic to constrain dcfifo(gray code pointer)?

For Grey counter there are two paths to consider:

i) clk1 to clk2 registers (async path): This will violate timing and set false path is essential to stop warnings or affect timing closure efforts.

ii) The synchroniser chain path (on same destination clock) This should pass timing though physically will be violated due to metastability.

MTBF can be reduced by some factors, one of them is that this path should have optimum slack. This is where controlling delay is helpful.

whether done in sdc command or fitter does it automaticlly.