Doh! My PLLs lose lock. Crosstalk?

I'm having a battle with my Cyclone II FPGA. I am using Quartus 9.1 web version to create a LVDS data deserialiser/sequencer for an industrial camera.

The image sensor has active and idle modes. In the active mode it passes image data, in idle mode it repeats the serial reference word that I use to align my deserialiser. There's no difference in word format or timing between these two modes.

I'm using megafunctions for PLL and comparator, I made my own deserialiser, because the Altera one didn't hit the spot for my design. I have enabled Timing Driven Synthesis and written a SDC file to describe the clock frequencies I am using.

So - I find that the output data turns to rubbish if there is a lot of image activity, but it is stable if the image is quiet. It is also OK when the sensor is in idle mode. I quickly discovered that the 12x PLL that multiplies the crystal clock is losing lock when picture is busy. Hold your hand over the lens, it stays locked. Let some light in, it loses lock (!)

OK, so I do away with the PLL, and use a high frequency crystal instead. Not my preferred option, but,hey I'm getting desperate. Even this method is not rock solid when the image gets busy.

Is it possible that I am getting crosstalk between signals inside the FPGA? Or perhaps some marginal timing? My design is almost completely pipelined, but needs to run from several different clock frequencies.

I am designing in VHDL, and I can't use the LogicLock feature on my version of Quartus. Are there any other tricks I can try to tighten up timing or internal routing? Is internal crosstalk a known problem?

TNX in advance...

Pete