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Altera_Forum's avatar
Altera_Forum
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14 years ago

Doh! My PLLs lose lock. Crosstalk?

I'm having a battle with my Cyclone II FPGA. I am using Quartus 9.1 web version to create a LVDS data deserialiser/sequencer for an industrial camera. The image sensor has active and idle mode...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

As previously explained, it's not cross talk inside the device. Your experience is almost reproducing what I reported in post# 7. The difference is however, that drive strength had been already reduced in our design.

Reducing the drive strength from maximum to minimum involves a considerable interference reduction as well, I think there's reason for hope.

But, when redesigning the board, why didn't you change to Cyclone III or IV? It can be expected to end the ground bounce/SSN related PLL unlock problems.

Regards,

Frank