Doh! My PLLs lose lock. Crosstalk?

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Hi there.

I begin to think the problem is deeper than the PLLs, because I still get data problems even when I don't use the PLL. I suspect some sort of data crosstalk inside the device. This seems a weird idea (after all my years designing with CPLDs) so I am open to any suggestions :)

Pete

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I very much doubt that. Cross talk inside FPGAs is something I never heard of though it is possible in theory.

I believe it is more likely you have clock domain transfer issues and possibly cross talk outside fpga.