Forum Discussion
Altera_Forum
Honored Contributor
14 years agoHi there.
Yes, that is possible. It's a custom board and I did not provide special filtering to the PLL power pins unfortunately. However I measured it and the local 3v3 power plane seems quite clean. I begin to think the problem is deeper than the PLLs, because I still get data problems even when I don't use the PLL. I suspect some sort of data crosstalk inside the device. This seems a weird idea (after all my years designing with CPLDs) so I am open to any suggestions :) Pete --- Quote Start --- Hi snaarman, do you use a custom board or an Altera Development Kit?? I ask you this because I had similar problem with the PLL in mine custom board and the problem was in the power supply. At the beginning of the project I used only one PLL and all worked fine, I discovered the problem when I added a second PLL. When the second one locked the clocks signal the first one lost the lock signal. I solve the problem modifying the clock frequencies of the second PLL to fit in the first one because, in my case, to change the power supply became too much expensive. I hope that this post can help you. --- Quote End ---