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Dangranla's avatar
Dangranla
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1 year ago
Solved

Doesn't generate CXL testbench for example design

Hi, As I follow the《Agilex™ 7 R-Tile Compute Express Link* (CXL*) 1.1/2.0 FPGA IP Design Example User Guide》generate the example desing. Trying to simulate the testbench withe VCS or Questsim, ...
  • RongY_altera's avatar
    RongY_altera
    1 year ago

    Hi,

    Please check if Questa tool is installed and EDA Tool Settings has Questa selected.


    Regards,

    Rong


RongY_altera's avatar
RongY_altera
Icon for Contributor rankContributor
1 year ago

Please try all English in project path, both your base project and the created one.


Regards,

Rong


Dangranla's avatar
Dangranla
Icon for New Contributor rankNew Contributor
1 year ago

Both of my project and created one are English path

Regards,

Wang