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Hi,
1.Yes compiler will omit the unused signals & block which have no connection logically to the Entity/module ports which can be seen in RTL viewer/also we can see it in chip planner LAB & LE.
2.But if we have unused ports in entity/module it will be a open net.
Please correct me if i'm wrong.
Thanks
Hari
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Once the design is compiled and fitted, there is no longer any concept of a block or module; everything has been flattened/smashed to just a bunch of logic.
So (2) is not quite correct; unused output ports of modules will have the logic driving them removed. There will never by any dangling unused outputs by default (unless the user specifically adds the compiler directives to preserve a specific node). Logic driving unused output ports of modules will be pruned back until all the nodes are used as an input to some cell.
It is not the case that entire modules are either included or removed; this optimization is pushed down to the individual logic cell level.
Not quite sure what you are trying to convey in point (1).
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