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This is not my experience. The compiler is smart enough to remove logic that is not used logically, so large portions of logic that for example drive a node that is never used may be optimized out of the design. Likewise, if some large block of logic ends up generating a constant result, it can be optimized down to a constant.
There are directives available that can be attached to signals / nodes in the source that specify that the attached node NOT be removed, but rather preserved, but this is the not the default. The compiler will aggressively remove unused logic unless explictly told not to by user directives.
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Hi,
1.Yes compiler will omit the unused signals & block which have no connection logically to the Entity/module ports which can be seen in RTL viewer/also we can see it in chip planner LAB & LE.
2.But if we have unused ports in entity/module it will be a open net.
Please correct me if i'm wrong.
Thanks
Hari
Honored Contributor
