Does Quartus supports Dynamic Array declaration?

No

I've been confused and frustrated with this as well. Sure, you wouldn't use dynmic arrays in implemented FPGA designs, but like you said a good chunk of the System Verilog constructs are there to support test benching and verification, and who doesn’t need to test or verify their FPGA designs? From what I can gather ModelSim had support in it years ago for dynamic arrays and most of the SV definition. So is it just the Altera version that doesn't support these features of SV?

As mentioned, there's a difference between synthesis and simulation. You can't dynamically change hardware while it's running (except when using an advanced feature, like partial reconfiguration). You can do and test anything you want in simulation, even if it can't be synthesized. HDLs were originally designed for simulation, so there's lots of stuff you can do in these languages that can't be synthesized.

I agree, but the question remains? Why doesn't the Altera version of ModelSim support those features of System Verilog that are there for simulation-only?

Dynamic arrays work just fine for me in modelsim altera 10.3d (the one from Q15).

module dyn_test;
  initial begin
    logic  dyna ;
    
    dyna = new;
    dyna = {0, 1, 2, 3};
    
    foreach(dyna) $display("%2h", dyna);
    
    dyna = new({dyna, 4,5,6,7});
    
    foreach(dyna) $display("%2h", dyna);
    
  end
  
endmodule

Thanks Tricky!