Does Quartus supports Dynamic Array declaration?

I've been confused and frustrated with this as well. Sure, you wouldn't use dynmic arrays in implemented FPGA designs, but like you said a good chunk of the System Verilog constructs are there to support test benching and verification, and who doesn’t need to test or verify their FPGA designs? From what I can gather ModelSim had support in it years ago for dynamic arrays and most of the SV definition. So is it just the Altera version that doesn't support these features of SV?