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KeyEng
New Contributor
New ContributorDoes Max 10 need "derive_pll_clocks" in constraint file
Below is from "Quartus® Prime Pro Edition User Guide": Note: Only Arria 10 and Cyclone® 10 GX devices support the Derive PLL Clocks (derive_pll_clocks) constraint. For all other supported devices, ...
KennyT_altera
Super Contributor
Super ContributorOnly Stratix 10, Agilex 7, and Agilex 5 devices do not require derive_pll_clocks in the .sdc file. For all other Intel FPGA devices, including MAX 10, the use of derive_pll_clocks is required unless PLL-generated clocks are explicitly constrained using create_generated_clock.
FvMDon't refer to Quartus Pro user guide for devices only supported by Quartus Standard.
