Division on the last outputs in vhdl

For division, i suggest using the divider ip core as it has pipelining. Using a divide function has no pipelining ability, so will give poor performance.

the only way to avoid divide by 0 error would be to not divide by 0.

You should also ask yourself whether you actually need to do the division at all.

Maybe you can rearrange the maths so it isn't needed.

If you don't need to do a division every clock, can you do a long division generating one bit every clock.

If absolute accuracy isn't required a 'multiply by reciprocal' could be used - especially if only dividing by a few known values.

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hi all,

counter count the number of input samples then the counter output (n) and i want to check if the numbers of samples is even do that (n*n) or if odd make that ((n*n)-1) will be something like that

signal dis : integer range 0 to 255 := 0;
 signal n   : integer range 0 to 255 :=0;  
if n mod 2=1 then    
   n_of samples<= ((n*n)-1);   
 else       n_of_samples <= n*n;  
 end if;    
 norm_dis <= dis / n_of_samples ;

(dis) signal will have values as (1,6,9,8,.....100) and the second signal (n) will have values as (0,2,8,9.......,200) and i want to fetch the two last outputs from the two signal (100,200) and divide 100/200.how can i write it in vhdl and how can overcome the divide by zero error.

i want help plz.

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Hi Basmahassan,

I don't see your description clear.

n is counter for number of samples. OK

to find out odd from even just check lsb 0 of n (if 0 it is even else it is odd) so you don't need mod function. No problem thus far.

but n*n & n*n-1 implies what? it will be square n and since dis is also 8 bits width then division will mostly be zero plus remainder.

Thus your description is not clear. It will help what actually you want to achieve, is'it about variance measurement or average ...etc.

The issue of just last sample is also hard to understand. if so what happens to previous samples. Or are you supposed to sum up all samples?

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thanks all; hi kaz n is not a vector value to check lsb to it and i use mod function because n is integer . if i understand wrong could you plz illustrate it for me. but n*n & n*n-1 implies what? it will be square n and since dis is also 8 bits width then division will mostly be zero plus remainder. why division will mostly be zero plus remainder. could you plz illustrate it too.

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You can declare (n) as unsigned(7 downto 0)

n range is 0~255 so n*n range is 0~65535, while (dis) range is 0~255 so if you divide dis/(n*n) you get (0~255)/(0~65536) and so it is mostly < 1 i.e. zero division result + remainder apart from the small range case when dis > (n*n)

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You can declare (n) as unsigned(7 downto 0)

n range is 0~255 so n*n range is 0~65535, while (dis) range is 0~255 so if you divide dis/(n*n) you get (0~255)/(0~65536) and so it is mostly < 1 i.e. zero division result + remainder apart from the small range case when dis > (n*n)

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hi kaz ,

sorry for late.i were very ill

anyway,y are right really the result of division will be always between 0~1. will be some thing like 0.234....etc.so its floating numbers, but i want to know from you how to avoid the floating numbers and the same time know the correct answer because you know that floating numbers in implementation is a big problem.

the counter will gave me the result of the data inputs number its only one value (the last value from a stream signal)

and the dis is the accumullation of the dis values its only one value and i want to check if the result of the counter is even or odd value then divide the accumulator result on the n*n or (n*n)-1 . i kknow its easy task ,but i new in vhdl and want your help .many thanks

--- Quote Start ---

hi kaz ,

sorry for late.i were very ill

anyway,y are right really the result of division will be always between 0~1. will be some thing like 0.234....etc.so its floating numbers, but i want to know from you how to avoid the floating numbers and the same time know the correct answer because you know that floating numbers in implementation is a big problem.

the counter will gave me the result of the data inputs number its only one value (the last value from a stream signal)

and the dis is the accumullation of the dis values its only one value and i want to check if the result of the counter is even or odd value then divide the accumulator result on the n*n or (n*n)-1 . i kknow its easy task ,but i new in vhdl and want your help .many thanks

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you can use lpm divider(not the floating point one).

alternatively if your n*n (& n*n-1) tolerates rounding to some power of 2 (2^k) then you can divide by discarding (k) LSBs but in this case you need to pre multiply (dis) value first by some large scale factor e.g. 2^10(add 10 leading zeros to dis value) then discard (k) lsbs. You will then know that your (dis) value is pre-scaled (thus you know where is the fractional point).