$display in synthesized SystemVerilog module

I wish generate assertion info or error and write code:

generate
    if ((WIDTH != 8) && (WIDTH != 14))
        $("Error in f_AmplCpx : parameter WIDTH is incorrect, found %d, should be 8 or 14", WIDTH);
endgenerate

and I've got error:

Error (10170): Verilog HDL syntax error at f_AmplCpx.sv near text: "$fatal";  expecting ";". Check for and fix any syntax errors that appear immediately before or at the specified keyword.

Using $display, Assert gives the same result.

How can I check parameters in synthesized code?