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Altera_Forum
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9 years ago

$display in synthesized SystemVerilog module

I wish generate assertion info or error and write code: generate if ((WIDTH != 8) && (WIDTH != 14)) $("Error in f_AmplCpx : parameter WIDTH is incorrect, found %d, should be 8 or 14"...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

$fatal only works in SystemVerilog. Do oyu have that enabled? It's possible that Altera does not support this yet.