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AEsqu's avatar
AEsqu
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5 years ago

Disable Quartus timing analyzer inverted clock

Hello, Is there a way to disable the inverted clock latch analysis in quartus 20.1 for arria 10? I had no such inverted clock analysis with the same design using Quartus 13.1 on stratix 3 , wit...
KennyT_altera's avatar
KennyT_altera
Icon for Super Contributor rankSuper Contributor
5 years ago

You need to look into your rtl viewer whether the launch and latch clock make sense. set false path will remove the analysis but it might cause functional failure if those path are valid analysis.


If you can provide us a rtl screenshot on those path will be good.


  • AEsqu's avatar
    AEsqu
    Icon for Contributor rankContributor
    5 years ago

    Quartus 20.1/arria 10 had too hard time to analyze the design with the test logic (test mode can then be enabled or not based on an input pin).

    There was no issue with Quartus 13.1/stratix 3 FPGA.

    I have the impression that Quartus 20.1 checks much more timings than Quartus 13.1 was (expecially those inverted checks).

    At the moment I disabled/removed the test logic to ease quartus place and route.