digital filter

hello everybody.

i am beginning with vhdl an i try to implement a digita filter on cyclone 2

This is the code i havebut i d ont understand why it doesnt work

thk for help

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

entity filter is

--generic ( FILTERLAENGE :natural:=6;

-- FILTERKOEFF :array (natural range 0 to FILTERLAENGE - 1) of signed( 7 downto 0) :=(-1,-1,-1,-1,-1,-1)

-- );

port (

clk : IN STD_LOGIC;

reset : IN STD_LOGIC;

filterGO : IN STD_LOGIC;

filterEingang : IN STD_LOGIC_VECTOR (15 downto 0);

filterAusgang : OUT STD_LOGIC_VECTOR (15 downto 0)

);

end;

architecture beh of filter is

constant FILTERLAENGE: natural := 6;

type t_memory is array (natural range 0 to FILTERLAENGE - 1) of signed(15 downto 0);

type t_Koeff is array (natural range 0 to FILTERLAENGE - 1) of signed( 7 downto 0);

constant FILTERKOEFF: t_Koeff := (to_signed(1, 8), to_signed(1, 8), to_signed(1, 8),

to_signed(1, 8), to_signed(1, 8), to_signed(1, 8));

signal Speicher: t_memory;

begin

process(clk, reset)

variable filterMult: signed(23 downto 0) := (others => '0');

variable filterSumme: signed(24 downto 0) := (others => '0');

begin

if (reset = '0') then

filterAusgang <= (others => '0');

Speicher <= (others => (others => '0'));

elsif (rising_edge(clk)) then

if (filterGO = '1') then

-- held samples from "filterEingang" stored in Speicher

for I in 0 to FILTERLAENGE - 2

loop

Speicher(I) <= Speicher(I + 1);

end loop;

Speicher(FILTERLAENGE - 1) <= signed(filterEingang);

-- filter operation y(n) = b0*x(n) + b1*x(n - 1) + ... + bn*x(0)

filterSumme := (others => '0');

for I in 0 to FILTERLAENGE - 1

loop

filterMult := FILTERKOEFF(I)*Speicher(FILTERLAENGE - (I + 1));

filterSumme:= filterSumme + resize(filterMult, 25);

end loop;

-- current filter result in "filterSumme" has 25 bits width

-- needed y(n) has to be a 16 bits data

filterAusgang <= std_logic_vector(resize(filterSumme, 16));

end if;

end if;

end process;

end beh;