Differential pins and clock constraints

You have constrained your DAC data with respect to DAC clk. That is enough.

The DAC clock itself can be set as false path because what matters is data relation to clk.

I note you have put zero delay. Normally you put +tSU and -tH of DAC(plus board effect) unless DAC does not need these constraints. In that case you will target minimum data skew (I suggest +50 ps, -50 ps instead of zeros).