Forum Discussion
kikoss
Occasional Contributor
Occasional ContributorDifferential CLK input handle
Hello I have a a differential clk come in to FPGA agilex7 F series Want to use it as a single clk to the design Iam using quartus 24 .1 pro Which good practice is recommended ? i see on a d...
- Hi,
yes. Same procedure for other differential in- and outputs.
kikossOccasional Contributor
Occasional ContributorYes , in the example i provide , I agree that this procedure should be applied to the FCO CLK or for the DCO CLK's that are connected to the inclock port (see figure)
But , for the rx_in_p and rx_in_n, the ALT LVDS ip called adc_controller (in the figure above) handle differential P and N legs ... so I understand that we must declare P and N as well on the RTL as separate ports . rigth ?
THX
