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kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
2 years ago
Solved

Differential CLK input handle

Hello I have a a differential clk come in to FPGA agilex7 F series Want to use it as a single clk to the design Iam using quartus 24 .1 pro Which good practice is recommended ? i see on a d...
Hdl
  • FvM's avatar
    FvM
    2 years ago
    Hi,
    yes. Same procedure for other differential in- and outputs.
kikoss's avatar
kikoss
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Hello

OK if i understand you correctly

  • you declare 1 port CLK on top level RTL module - let say FCO_CLK (even if its differential from the ADC)
  • use this port on the RTL , for PLL input etc..
  • assign FCO_CLK only to P leg on assignment editor (and not assigning at all N leg)
  • let the fitter do the job for N leg

Thats rigth ?

THX

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    2 years ago
    Hi,
    yes. Same procedure for other differential in- and outputs.