Forum Discussion
kikoss
Occasional Contributor
Occasional ContributorDifferential CLK input handle
Hello I have a a differential clk come in to FPGA agilex7 F series Want to use it as a single clk to the design Iam using quartus 24 .1 pro Which good practice is recommended ? i see on a d...
- Hi,
yes. Same procedure for other differential in- and outputs.
FvM
Super Contributor
Super ContributorHi,
I know how an ADC LDVS interface looks like, I'm working with it since 15 years or so. Here's an example how I configure clock and data interface for AD9222, in this case I'm using FCO rather than DCO and a PLL to generate bit clock.
top entity port definition
ADC_CLK : OUT STD_LOGIC;
ADC_FCO : IN STD_LOGIC;
ADC_LVD : IN STD_LOGIC_VECTOR(1 TO 8);
assigned IO standards
set_instance_assignment -name IO_STANDARD LVDS -to ADC_LVD*
set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
set_instance_assignment -name IO_STANDARD LVDS -to ADC_LCLK
If you review Intel documents, you'll realize that this is the suggested way to implement differential in- and outputs.
set_instance_assignment -name IO_STANDARD LVDS -to ADC_LVD*
set_instance_assignment -name IO_STANDARD LVDS -to ADC_FCO
set_instance_assignment -name IO_STANDARD LVDS -to ADC_LCLK
If you review Intel documents, you'll realize that this is the suggested way to implement differential in- and outputs.
- FvMForgot to mention that single-ended port signal is assigned to positive pin of the differential pair, corresponding negative pin is assigned by fitter automatically.
