Forum Discussion
kikoss
Occasional Contributor
Occasional ContributorDifferential CLK input handle
Hello I have a a differential clk come in to FPGA agilex7 F series Want to use it as a single clk to the design Iam using quartus 24 .1 pro Which good practice is recommended ? i see on a d...
- Hi,
yes. Same procedure for other differential in- and outputs.
kikossOccasional Contributor
Occasional ContributorHi
To be clearer , what i meant, is that i have a differential clk that comes into the fpga , from an adc converter
I want to use this clock for the ALT_LVDS ip , and this IP is able to receive only single ended clk as we see here
How to handle that in quartus ?
Thx
FvMSuper Contributor
Hi,
input and output ports of design modules and top level interface always appear as single ended signal, except for rarely used special differential IO low-level primitives. You make the port a differential in- or output by assigning a differential IO standard (e.g. LVDS) in pin planner or assignment editor to it.
