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Altera_Forum's avatar
Altera_Forum
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18 years ago

Different simulated results with block and verilog coding

I am integrating a project by combining different blocks which were created by different programmers. Prior to the combining, these blocks each were verilog / VHDL files that produce desirable simula...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi guys, thanks a lot for your kind help. I have relooked and tested my code, and it appears that upon combining the blocks, there are some coding errors. I have proceeded to fix those errors and am getting what I desire for now. I'd say your opinions very much assist me in my troubleshooting as I am still quite new to the Quartus II development environment. Shall try out the RTL viewer. Will post questions if I encounter any.