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Altera_Forum's avatar
Altera_Forum
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18 years ago

Different simulated results with block and verilog coding

I am integrating a project by combining different blocks which were created by different programmers. Prior to the combining, these blocks each were verilog / VHDL files that produce desirable simula...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hi,

If I was you I would use the following option in Quartus

Tools -> Netlist Viewer -> RTL viewer.

this can be performed after analysis and elaboration.

This will tell you whether you have connected up your blocks correctly through the use of port maps in your VHDL. floating inputs will cause logic to be optimised away. Also check outputs are connected to other blocks

The other way is too simulate this, ie if you have floating inputs then this will be evident from the waveforms in modelsim

Regards