Different simulated results with block and verilog coding

Hello,

if it would be some kind of problem as I suggested (missing connections), it should be recognizable from Quartus warnings, but may be not easily. But I believe, such a case can also be identified by thorougly tracking the signal flow on a paper or in mind.

One general debug option is a Modelsim simulation of full design. With graphic top level, this requires creating a HDL file for top level, but that's easy and also a testbench for the full design, may be more effort, depending on the designs pin count. In ModelSim, you can more easily watch internal signals during simulation than with Quartus simulator. The other option is to use SignalTap, but it can't obviously watch signals that have been removed in optimization.

Regards,

Frank