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Altera_Forum
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18 years ago

Different simulated results with block and verilog coding

I am integrating a project by combining different blocks which were created by different programmers. Prior to the combining, these blocks each were verilog / VHDL files that produce desirable simula...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Hi FvM, thank you so much for viewing into my problem. My meaning of truncating the code is as you said, not synthesized.

I am suspecting my coding could be the problem. Do you have any suggestion as good methods to troubleshoot the coding in this situation: where the code synthesizes properly under a verilog/VHDL form, and does not get synthesized under combined block diagram form?