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Altera_Forum's avatar
Altera_Forum
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14 years ago

different result when compiling asram.v with quartus ii v9.1 and quartus ii v10.1

I want to compile the verilog source code of one async ram. The code shows below:

module asram(a,io,ce_,oe_,we_,lb_,ub_);

parameter dqbits=16;

parameter memdepth=255;

parameter addbits=7;

parameter taa=10;

parameter toha=3;

parameter thzce=4;

parameter tsa=2;

parameter thzwe=5;

input ce_,oe_,we_,lb_,ub_;

input [(addbits-1):0]a;

inout[(dqbits-1):0]io;

wire [(dqbits-1):0]dout;

reg [(dqbits/2-1):0]bank0[0:memdepth];

reg [(dqbits/2-1):0]bank1[0:memdepth];

wire r_en=we_ &(~ce_) & (~oe_);

wire w_en=(~we_)&(~ce_)&((~lb_)|(~ub_));

assign# (r_en?taa:thzce)io=r_en?dout:16'bz;

assign dout[(dqbits/2-1):0] = lb_?8'bz:bank0[a];

assign dout[(dqbits-1):(dqbits/2)] = ub_?8'bz:bank1[a];

always@(a or w_en)

begin

# tsa

if(w_en)

# thzwe

begin

bank0[a]=lb_?bank0[a]:io[(dqbits/2-1):0];

bank1[a]=ub_?bank1[a]:io[(dqbits-1):(dqbits/2)];

end

end

endmodule

When compiling with quartus ii v10.1, the result functions error. The resource it occupys like below:

combinational aluts 18 / 424,960 ( < 1 % )

memory aluts 0 / 212,480 ( 0 % )

dedicated logic registers 0 / 424,960 ( 0 % )

device ep4se530f43c4

timing models final

logic utilization < 1 %

When compiling with quartus ii v9.1, the result functions correctly. The resource it occupys like below:

combinational aluts 2,854/ 424,960 ( < 1 % )

memory aluts 0 / 212,480 ( 0 % )

dedicated logic registers 0 / 424,960 ( 0 % )

device ep4se530f43c4

timing models final

logic utilization < 1 %

Obviously, the number of ALUTs used is different. Can anyone tell me why?

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    What do you want to achieve? This is a RAM simulation model, not suited for synthesis.

    P.S.: Apart from the fact, that your design is effectively unsynthesizable Verilog, the different compilation behaviour should be explained. There's something strange in Quartus 10 and 11. If you look to the RTL netlist, two instances of ASYNC_RAM are inferred from the code. I'm not sure, if the asynchronous RAM block is a new feature in Quartus, but it's not supported by any recent FPGA and silently discarded in the Quartus 10/11 synthesis.

    If you disable Auto RAM Replacement in the Quartus synthesis options, you get the RAM synthesized in logic cells as in Quartus 9.

    A huge number of unsafe latch behaviour warnings is telling you, that the design isn't synthesizable.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    Thanks FvM.

    When disable Auto RAM Replacement, the result comiled with Quartus 10 is the same as Quartus 9.